I think this would be seen as an overly-leaky abstraction, for several reasons: (1) You don't want the chip's correctness to be at the mercy of the particular i

I think this would be seen as an overly-leaky abstraction, for several reasons: (1) You don't want the chip's correctness to be at the mercy of the particular instruction stream it's given; (2) the problem is potentially solvable at the microcode level, which makes (1) remain viable. But, if such "hint" ops were seen as the only viable way to get correct, high-performance behavior in these cases, and there was a commercial case to be made for it, I could see processor vendors adding them to the IA.