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We do not yet support AMD's nested implementation (we do on Intel). But cvallejo is also the PM for Nested :). As for 224, we've always reserved threads on eac
by boulos 7y ago
We do not yet support AMD's nested implementation (we do on Intel). But cvallejo is also the PM for Nested :).
As for 224, we've always reserved threads on each host for I/O and so on. Figure 2 from the Snap paper [1] is probably the best public reference. We also don't make it clear (on purpose) what size the underlying host processors are, though you can clearly guesstimate pretty easily.
[1] https://research.google/pubs/pub48630/ https://research.google/pubs/pub48630/
- QUFB 7y agoSpeaking of nested virtualization, are there any plans to support this on E2, or will we have to use other instance types?
- boulos 7y agoThe blocker here would be the need for supporting nested on AMD parts (as E2 can choose between Intel and AMD parts).
- JoshTriplett 7y ago> We do not yet support AMD's nested implementation (we do on Intel). Any particular reason for that limitation, or just "not implemented yet"? (Not asking for product roadmaps, just wondering if there's a specific technical issue that makes it more difficult to support.) > As for 224, we've always reserved threads on each host for I/O and so on. Figure 2 from the Snap paper [1] is probably the best public reference. That's helpful, thank you.
- boulos 7y agoNot implemented yet. In the stack rank of “stuff needed to update our hypervisor for AMD again” it wasn’t at the top :). Note the again as well: GCE originally had it such that N in N1 meant iNtel, and A1 was for AMD (as Joe said publicly here: https://twitter.com/jbeda/status/1159891645531213824 https://twitter.com/jbeda/status/1159891645531213824). By the time I joined though, we didn’t see the point of the A1 parts, since the Sandybridge’s smoked them.