2 ms·
> Floating point division can cost you more cycles, both in latency and throughput No, on Ryzen, 32-bit float division, divps instruction, has latency 10 cycle
by Const-me 7y ago
> Floating point division can cost you more cycles, both in latency and throughput
No, on Ryzen, 32-bit float division, divps instruction, has latency 10 cycles, throughput 3 cycles. 64-bit float division, divpd instruction, has latency up to 13, throughput up to 5. Both faster than a cache miss, in latency and especially throughput.
> Even just plain old L3 latency can be worse than misprediction.
Yes. BTW, the slowest thing that can happen on modern CPU is not L3 access, it’s access to a cache line modified by another CPU core. Even slower than main memory latency.