5 ms·

> An incorrectly predicted branch is one of the slowest things you can have happen on a modern CPU Per Agner Fog, misprediction on Ryzen will cost you 18 cyc

> An incorrectly predicted branch is one of the slowest things you can have happen on a modern CPU Per Agner Fog, misprediction on Ryzen will cost you 18 cycles. On Haswell family, 15 to 20. Floating point division can cost you more cycles, both in latency and throughput. Even just plain old L3 latency can be worse than misprediction.

jupp0r 7y ago
That’s oversimplified. If the falsely predicted branch issues a load instruction for example, you might use up valuable memory bandwidth, trash cache lines, etc. There are way more side effects that can make false branch predictions more expensive. It’s also extremely microarchitecture dependent, proprietary and undocumented what exactly happens, which is why we need to benchmark the actual code under consideration.
- gpderetta 7y ago
  Yes. Also a misprediction affects all instructions in flight after the branch, a floating point operation or slow load only affects instructions that depend on it.
Const-me 7y ago
> Floating point division can cost you more cycles, both in latency and throughput No, on Ryzen, 32-bit float division, divps instruction, has latency 10 cycles, throughput 3 cycles. 64-bit float division, divpd instruction, has latency up to 13, throughput up to 5. Both faster than a cache miss, in latency and especially throughput. > Even just plain old L3 latency can be worse than misprediction. Yes. BTW, the slowest thing that can happen on modern CPU is not L3 access, it’s access to a cache line modified by another CPU core. Even slower than main memory latency.
gpderetta 7y ago
> plain old L3 latency can be worse than misprediction. true but the instruction fetcher is driven by the branch predictor, so a misprediction to rarely executed code in practice also implies a cache miss.

5 ms·

> An incorrectly predicted branch is one of the slowest things you can have happen on a modern CPU Per Agner Fog, misprediction on Ryzen will cost you 18 cyc

by akira2501 7y ago

jupp0r 7y ago
That’s oversimplified. If the falsely predicted branch issues a load instruction for example, you might use up valuable memory bandwidth, trash cache lines, etc. There are way more side effects that can make false branch predictions more expensive. It’s also extremely microarchitecture dependent, proprietary and undocumented what exactly happens, which is why we need to benchmark the actual code under consideration.
- gpderetta 7y ago
  Yes. Also a misprediction affects all instructions in flight after the branch, a floating point operation or slow load only affects instructions that depend on it.
Const-me 7y ago
> Floating point division can cost you more cycles, both in latency and throughput No, on Ryzen, 32-bit float division, divps instruction, has latency 10 cycles, throughput 3 cycles. 64-bit float division, divpd instruction, has latency up to 13, throughput up to 5. Both faster than a cache miss, in latency and especially throughput. > Even just plain old L3 latency can be worse than misprediction. Yes. BTW, the slowest thing that can happen on modern CPU is not L3 access, it’s access to a cache line modified by another CPU core. Even slower than main memory latency.
gpderetta 7y ago
> plain old L3 latency can be worse than misprediction. true but the instruction fetcher is driven by the branch predictor, so a misprediction to rarely executed code in practice also implies a cache miss.