The Alpha did have a memory model that was weaker in some respects than pretty much every other RISC CPU. I'm not clear on the details, but I think that one of

The Alpha did have a memory model that was weaker in some respects than pretty much every other RISC CPU. I'm not clear on the details, but I think that one of them is described in https://www.kernel.org/doc/Documentation/memory-barriers.txt https://www.kernel.org/doc/Documentation/memory-barriers.txt in the 'GUARANTEES' section -- if you do "Q = LOAD P; D = LOAD *Q" then on Alpha and only on Alpha extra barriers are required to ensure that the second memory access (whose address depends on the result of the first load) really does get issued in-order after the first.