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So at the consumer level, DDR2[popular standard c. 2005] could be clocked up to 266 MHz whereas DDR4[popular now] clocks in at 1600MHz. So a little more than a
by dwrodri 7y ago
So at the consumer level, DDR2[popular standard c. 2005] could be clocked up to 266 MHz whereas DDR4[popular now] clocks in at 1600MHz. So a little more than a 6x speedup in transaction times. Unlike processors, whose features make it quite difficult to compare against each other, DRAM has stayed relatively straightforward: its still just a bunch of densely packed flip-flops connected to a memory controller that offers bank-strided column/row access.
As you can imagine, processor performance has grown a lot more than 6x over the years. The amount of cores in a package alone has increased more than 6x! So how do we get around this?
1) Larger caches: the most efficient optimization to any slow task is to simply not perform said task. Having a larger L3 cache means sending requesting fewer pages from DRAM.
2) “Hiding” latency with bandwidth: if I have to incur a (relatively) large time penalty tp go to DRAM, I better make sure to make it worth my time. Instead of always getting data in 4KiB pages, often times modern processors support “superpages” all the way up to the gigabytes. If you’re going to go drive out to the store, it makes sense to buy groceries for the week instead of just the candy bar you’re craving right now, right? That way when you actually have to cook the work has already been done.
I am probably missing some nuance here, especially when it comes to memory controllers and putting caches on DRAM, but this is the gist.
- vbezhenar 7y agoBut frequency of RAM and latency is not the same. DDR2-800 can have something like 4-4-4-12 timings, while DDR4-2666 can have something like 15-17-17-35 timings. So their result latency will be around the same! And those numbers I just googled, I did not made them up.
- Retric 7y agoDDR2 vs DDR4 has effectively zero impact on latency. Due to the physical distances between RAM modules and the CPU, that’s been stuck within a narrow range for decades. https://en.wikipedia.org/wiki/CAS_latency https://en.wikipedia.org/wiki/CAS_latency The specific implication details make a difference, but nothing is going to provide a 4x improvement in latency so other considerations take precedence. The real change is ever growing cache sizes allowing CPU’s to minimize random RAM reads.
- mantap 7y agoIs there a reason why they don't package a couple GB of DRAM in there?
- Retric 7y agoActually yes, the cache hit ratio is not linear with cache size so you get diminishing returns. http://www.dataram.com/blog/?p=112 http://www.dataram.com/blog/?p=112. On top of this, once a CPU core is operating at say 80% of the time the maximum possible speed up from more cache is 20%. Further, every layer of cache adds latency and cost as you need to check it before going to main memory. In the 486 and early pentium days External Cache was common, but it’s no longer useful.
- mantap 7y agoI had something more like a swap than a cache in mind. Expose it as additional physical address space and let the OS decide which pages live there vs main memory.
- coretx 7y agoYes. The very same reason why they waited years before they eventually moved the memory controller on to the CPU die. It's expensive m2 real estate and eats a big chunk of the waffer. Furthermore, there is diminishing returns regarding all kinds of cache. Most of the recent performance increases are attributed to the very dangerous practice called branche prediction.
- rasz 7y agoCAS has nothing to do with "distances between RAM modules and the CPU".
- Retric 7y agoThe memory controller referenced in CAS is in the CPU and the ram modules are part of those ram sticks so it’s not the only component of CAS latency but it is a big one. “For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.”
- zajio1am 7y ago> Instead of always getting data in 4KiB pages, often times modern processors support “superpages” all the way up to the gigabytes. Page size is irrelevant for purposes of getting data from RAM to CPU / cache. This is done by cacheline size, which is usually 64 B. Higher page size helps with better TLB efficiency and also for disk to RAM copy (if that is strictly page-based).
- dwrodri 7y agoUpdate: I was wrong about pages, but the fundamental notion that we're moving towards "solving" latency issues with bandwidth hasn't changed. Paging strategies don't change CAS timing (which is what I should have replied with), but your CAS timings are only half of the equation, hence my emphasis on bandwidth.