4 ms·
Yeah, this should be roughly the same overhead as an ADD: LEA rDest, [rBase + 8*rPtr] (The "load effective address" instruction computes an effective addr
by cfallin 7y ago
Yeah, this should be roughly the same overhead as an ADD:
LEA rDest, [rBase + 8*rPtr]
(The "load effective address" instruction computes an effective address like a load or store would, but just gives the address without doing a memory access.)
- the8472 7y agoAIUI mov supports these things directly[0] and if I read the instruction tables correctly then at least on skylake the latency/throughput is the same for all addressing modes[1] [0] http://www.c-jump.com/CIS77/ASM/Addressing/lecture.html#R77_0060_scaling_factors http://www.c-jump.com/CIS77/ASM/Addressing/lecture.html#R77_... [1] https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf (page 238)