> Above all, the original plan for RISC-V was to make a barebone MCU ISA first, and everything else second. This is simply not correct. RISC-V was designed to

> Above all, the original plan for RISC-V was to make a barebone MCU ISA first, and everything else second. This is simply not correct. RISC-V was designed to allow minimal cores but by design it also tried to cover everything from minimal to HPC. > This was largely to ARM being very militant with terms on RTL access for M* series cores for commercial use. Again this is not correct. Are you just making this stuff up? The reason they developed RISC-V is because of complexity and license issues that would not allow them tape out say x86 or ARM. > If you throw enough extension, and workarounds even on top of 8051, you should be able to make a CPU grade core with it. But you being able to do it, doesn't mean you should. Why not? Is your instruction gone run slower because it spec is written down in a different PDF document? Are you mixing up ISA and micro-architecture? If you take the whole RV64GCVBH you have a full featured core that is designed to allow super high performance implementation. And the ISA design is easily better then any of the other ISAs.