6 ms·

It’s a real shame avx-512 has so many eccentricities when it’s a much nicer ISA than anything before it (in x86 land). I would almost prefer a more predictable

by oddity 7y ago

It’s a real shame avx-512 has so many eccentricities when it’s a much nicer ISA than anything before it (in x86 land). I would almost prefer a more predictable, high-latency decomposition into 4x128 wide uops over what we have now.

zwegner 7y ago
But what about instructions like vpermi2b, which does 64 parallel 128 byte table lookups? The AVX shuffle instructions were hamstrung by the split into two 16-byte halves...
- BeeOnRope 7y ago
  Yeah, the shuffles are awesome in AVX-512.
dman 7y ago
Intel really botched the launch of AVX-512. By not making it available on client, and even on server having it be available on select chips meant that no one code coded / optimized for it. If you are proposing new instructions make sure they are widely available.
- xscott 7y ago
  Additionally, it looks like each subset of AVX-512 past the foundation is an optional feature and needs to be tested for. With only a few exceptions (usually as a result of bickering between Intel and AMD), previous ISA extensions implied you had everything that came before it too. In practice this means you could pick a few entire subsets: Legacy+SSE2 is always there for 64 bit, maybe test up to SSE4.2 for another subset. Maybe switch everything from REX to VEX if it has AVX and AVX2. That's effectively three back ends, which is manageable. With AVX-512, everything beyond AVX-512F is a la carte, and that adds unwanted complexity for instruction selection in a compiler. Just look at all the separate AVX feature flags from CPUID: https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_F... Between the performance problems and complexity, I think it'll be a while until AVX-512 is attractive.
  - BeeOnRope 7y ago
    Although there are many AVX-512 features, actual implementations still break down into only a few subsets. If you ignore the EOL Xeon Phi stuff (with different and incompatible ISAs), it was proceeding in a superset approach, but cascade lake and cooper lake AI extensions kind of messed that up. Good way to visualize it: https://github.com/InstLatx64/InstLatx64/raw/master/VennDiagrams/Venn_AVX512_v141.png https://github.com/InstLatx64/InstLatx64/raw/master/VennDiag... Basically you have the SKX subset and the ICL as the big important ones in the near future, unless you care about AI, in which case Cascade Lake is like SKX + VNNI and Cooper Lake is additionally + BF16. So in practice you'll target one of those subsets, nothing more fine-grained that that. Yes you should still test for all the required extensions, but that part is easy.
    - xscott 7y ago
      That's a great picture (thank you), but it really looks complicated to me. :-)
      - BeeOnRope 7y ago
        It's complicated yes, but it doesn't approach the level of thinking about all 20 AVX-512 extensions individually and testing for them. Basically, on the ground, it is about as complicated as say the few 128 and 256 but extensions: there are only a few sets of functionality you have to care about (2 if you don't care about AI). It's just that within those groups Intel decided to be very fine grained about the functionality, dividing the instructions among many flags (still, in a logical way). So instead of the new generation just supporting SSE2, say, it supports 6 new flavors of AVX-512. My claim then is that this doesn't matter much: you can just think of all of those 6 as a unit, AVX-512-ICELAKE or whatever, because there are no CPUs that support a proper subset and there probably never will be (if there is, that's fine - you'll evaluate then if it makes sense for a new codepath). Maybe I'm not making a good case that this is same :).
        xscott 7y ago
        Nah, you're making a good case. I think what you're trying to say is to test the CPUID bits for a consistent subset of AVX512 flags and treat it all as one or two clumps. There was always going to be a fallback path for older subsets (SSE2-SSE4.2, AVX1-AVX2) anyways, so punt if it doesn't have all the features in a clump.
- inetknght 7y ago
  As a developer who's micro-optimized some genetic software, I can confirm that I'd considered AVX-512 but decided against it after learning that the hardware being purchased by the company would not have the full AVX-512 feature set desired and it was simpler/easier to just write it in AVX2. Getting the software to also work on older/cheaper hardware made the business owner happy too.
  - BeeOnRope 7y ago
    Which ISA did it have? Even the minimal AVX-512 ISA on any mainstream CPU (SKX) is pretty much a strict superset of AVX2.
    - inetknght 7y ago
      > Which ISA did it have? Business side was considering whether to buy Skylake or Broadwell.
  - eyegor 7y ago
    If you really care about performance, you could always compile on the target machine directly via -xhost [0] or whatever the flag is on your compiler. [0] https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xhost-qxhost https://software.intel.com/en-us/cpp-compiler-developer-guid...
    - inetknght 7y ago
      In my case, it's GCC. The option is `-march=native -mtune=native`. The trick though is _describing_ the scalar operations in the language and getting the compiler to understand how to efficiently vectorize them. I couldn't get GCC to do it at the time (GCC-5 if I recall, though we deployed with GCC-6); maybe it was just inexperience on my part. But I ended up writing the intrinsics by hand. To be quite honest it was my first dive into SIMD and I thought it was rather fun to do.
      - ncmncm 7y ago
BeeOnRope 7y ago
If I could choose, I would like everything to run at the max turbo frequency all the time, yeah. Still, and despite writing this post which will make a lot of people express something similar to what you wrote, I consider myself an AVX-512 fan, not the other way around. It's the most important ISA extension since, well, I'm not sure: a long time (probably AVX and AVX/2 combined would have a similar impact). It introduces a whole ton of stuff that is very powerful: full-width shuffles down to byte granularity with awesome performance, masking of every operation, often free, compress and expand operations, and a longer list at [1]. That's only from an integer angle too (what I care about). Yeah, it's taken AVX-512 a while to get traction (the fact that generation after generation of new chips have just been Skylake client derivatives with no AVX-512 hasn't helped), but I hope we are reaching a turning point. These transitions are something you have to deal with if you want max performance, and I think we'll come up with better models for how to make the "global" decision of whether you should be using AVX-512. --- [1] https://branchfree.org/2019/05/29/why-ice-lake-is-important-a-bit-bashers-perspective/ https://branchfree.org/2019/05/29/why-ice-lake-is-important-...
- ComputerGuru 7y ago
  The never-ending Skylake is/was a real problem. Intel was slowly adding features in a manner where it made sense to target last n generations but then all that came to a perpetual stop and suddenly we have this new extension that you can only really use on the very latest and most expensive, with virtually no backwards compatibility. The instructions are sufficiently different from AVX2 that any appropriate use is not as simple as sticking it behind a gate and using a smaller block size, it basically requires a completely separate (re)write to properly take advantage of.
  - BeeOnRope 7y ago
    > The instructions are sufficiently different from AVX2 that any appropriate use is not as simple as sticking it behind a gate and using a smaller block size, it basically requires a completely separate (re)write to properly take advantage of. I'd say yeah, you often need a rewrite of the core loop to take full advantage, but you can still more or less write AVX-style code in AVX-512 if you want, and take advantage of the width increase. The main difference I think for most code is the way the comparison operators compare into a mask register. It would have been nice if they had just extended the existing compare into SIMD reg (0/-1 result) instructions too, to ease porting.
chx 7y ago
> it’s a much nicer ISA than anything before it (in x86 land). It's coming from Intel Knights Landing. Previous massively multicore Intel offerings used a Pentium core and had a different 512 bit SIMD instruction set, KL used a Silvermont Atom core and introduced AVX-512 and parts of it were implemented in the Skylake Purley platform in a desperate attempt to give KL more software. With little to no actual adaption and the desperate situation of being stuck on 14nm and overselling those capabilities because they expected most CPUs to move over to 10nm it was no surprise the Knights... chips got the axe. But, the insanity of AVX-512 having an entire menu of possible instruction subsets stayed.
- zwegner 7y ago
  Note that the 512-bit Larrabee instructions (on Knight's Ferry/Corner) had different encodings (and IIRC different encodings between KNF and KNC), but it was essentially the same instruction set. The few differences there were between LRBNI and AVX-512 had (AFAIK) almost nothing to do with the move from the old Pentium in-order core to Silvermont. I think it's also safe to assume that, given the lead time to design an ISA and integrate it into an architecture (many years), the merging of AVX-512 into Skylake wasn't done "in a desperate attempt to give KL more software". These slides from Tom Forsyth provide lots of interesting background on the evolution of the instructions: http://tomforsyth1000.github.io/papers/LRBNI%20origins%20v4%20full%20fat.pdf http://tomforsyth1000.github.io/papers/LRBNI%20origins%20v4%...
Nyan 7y ago
> I would almost prefer a more predictable, high-latency decomposition into 4x128 wide uops over what we have now. AVX512-VL gives the programmer AVX512 functionality at 128/256-bit widths, if it is believed to be more beneficial than a frequency hit.

by oddity 7y ago

zwegner 7y ago

But what about instructions like vpermi2b, which does 64 parallel 128 byte table lookups? The AVX shuffle instructions were hamstrung by the split into two 16-byte halves...

BeeOnRope 7y ago
Yeah, the shuffles are awesome in AVX-512.

dman 7y ago

Intel really botched the launch of AVX-512. By not making it available on client, and even on server having it be available on select chips meant that no one code coded / optimized for it. If you are proposing new instructions make sure they are widely available.

xscott 7y ago
Additionally, it looks like each subset of AVX-512 past the foundation is an optional feature and needs to be tested for. With only a few exceptions (usually as a result of bickering between Intel and AMD), previous ISA extensions implied you had everything that came before it too. In practice this means you could pick a few entire subsets: Legacy+SSE2 is always there for 64 bit, maybe test up to SSE4.2 for another subset. Maybe switch everything from REX to VEX if it has AVX and AVX2. That's effectively three back ends, which is manageable. With AVX-512, everything beyond AVX-512F is a la carte, and that adds unwanted complexity for instruction selection in a compiler. Just look at all the separate AVX feature flags from CPUID: https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_F... Between the performance problems and complexity, I think it'll be a while until AVX-512 is attractive.
- BeeOnRope 7y ago
  Although there are many AVX-512 features, actual implementations still break down into only a few subsets. If you ignore the EOL Xeon Phi stuff (with different and incompatible ISAs), it was proceeding in a superset approach, but cascade lake and cooper lake AI extensions kind of messed that up. Good way to visualize it: https://github.com/InstLatx64/InstLatx64/raw/master/VennDiagrams/Venn_AVX512_v141.png https://github.com/InstLatx64/InstLatx64/raw/master/VennDiag... Basically you have the SKX subset and the ICL as the big important ones in the near future, unless you care about AI, in which case Cascade Lake is like SKX + VNNI and Cooper Lake is additionally + BF16. So in practice you'll target one of those subsets, nothing more fine-grained that that. Yes you should still test for all the required extensions, but that part is easy.
  - xscott 7y ago
    That's a great picture (thank you), but it really looks complicated to me. :-)
    - BeeOnRope 7y ago
      It's complicated yes, but it doesn't approach the level of thinking about all 20 AVX-512 extensions individually and testing for them. Basically, on the ground, it is about as complicated as say the few 128 and 256 but extensions: there are only a few sets of functionality you have to care about (2 if you don't care about AI). It's just that within those groups Intel decided to be very fine grained about the functionality, dividing the instructions among many flags (still, in a logical way). So instead of the new generation just supporting SSE2, say, it supports 6 new flavors of AVX-512. My claim then is that this doesn't matter much: you can just think of all of those 6 as a unit, AVX-512-ICELAKE or whatever, because there are no CPUs that support a proper subset and there probably never will be (if there is, that's fine - you'll evaluate then if it makes sense for a new codepath). Maybe I'm not making a good case that this is same :).
      - xscott 7y ago
        Nah, you're making a good case. I think what you're trying to say is to test the CPUID bits for a consistent subset of AVX512 flags and treat it all as one or two clumps. There was always going to be a fallback path for older subsets (SSE2-SSE4.2, AVX1-AVX2) anyways, so punt if it doesn't have all the features in a clump.
inetknght 7y ago
As a developer who's micro-optimized some genetic software, I can confirm that I'd considered AVX-512 but decided against it after learning that the hardware being purchased by the company would not have the full AVX-512 feature set desired and it was simpler/easier to just write it in AVX2. Getting the software to also work on older/cheaper hardware made the business owner happy too.
- BeeOnRope 7y ago
  Which ISA did it have? Even the minimal AVX-512 ISA on any mainstream CPU (SKX) is pretty much a strict superset of AVX2.
  - inetknght 7y ago
    > Which ISA did it have? Business side was considering whether to buy Skylake or Broadwell.
- eyegor 7y ago
  If you really care about performance, you could always compile on the target machine directly via -xhost [0] or whatever the flag is on your compiler. [0] https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xhost-qxhost https://software.intel.com/en-us/cpp-compiler-developer-guid...
  - inetknght 7y ago
    In my case, it's GCC. The option is `-march=native -mtune=native`. The trick though is _describing_ the scalar operations in the language and getting the compiler to understand how to efficiently vectorize them. I couldn't get GCC to do it at the time (GCC-5 if I recall, though we deployed with GCC-6); maybe it was just inexperience on my part. But I ended up writing the intrinsics by hand. To be quite honest it was my first dive into SIMD and I thought it was rather fun to do.
    - ncmncm 7y ago

BeeOnRope 7y ago

If I could choose, I would like everything to run at the max turbo frequency all the time, yeah. Still, and despite writing this post which will make a lot of people express something similar to what you wrote, I consider myself an AVX-512 fan, not the other way around. It's the most important ISA extension since, well, I'm not sure: a long time (probably AVX and AVX/2 combined would have a similar impact). It introduces a whole ton of stuff that is very powerful: full-width shuffles down to byte granularity with awesome performance, masking of every operation, often free, compress and expand operations, and a longer list at [1]. That's only from an integer angle too (what I care about). Yeah, it's taken AVX-512 a while to get traction (the fact that generation after generation of new chips have just been Skylake client derivatives with no AVX-512 hasn't helped), but I hope we are reaching a turning point. These transitions are something you have to deal with if you want max performance, and I think we'll come up with better models for how to make the "global" decision of whether you should be using AVX-512. --- [1] https://branchfree.org/2019/05/29/why-ice-lake-is-important-a-bit-bashers-perspective/ https://branchfree.org/2019/05/29/why-ice-lake-is-important-...

ComputerGuru 7y ago
The never-ending Skylake is/was a real problem. Intel was slowly adding features in a manner where it made sense to target last n generations but then all that came to a perpetual stop and suddenly we have this new extension that you can only really use on the very latest and most expensive, with virtually no backwards compatibility. The instructions are sufficiently different from AVX2 that any appropriate use is not as simple as sticking it behind a gate and using a smaller block size, it basically requires a completely separate (re)write to properly take advantage of.
- BeeOnRope 7y ago
  > The instructions are sufficiently different from AVX2 that any appropriate use is not as simple as sticking it behind a gate and using a smaller block size, it basically requires a completely separate (re)write to properly take advantage of. I'd say yeah, you often need a rewrite of the core loop to take full advantage, but you can still more or less write AVX-style code in AVX-512 if you want, and take advantage of the width increase. The main difference I think for most code is the way the comparison operators compare into a mask register. It would have been nice if they had just extended the existing compare into SIMD reg (0/-1 result) instructions too, to ease porting.

chx 7y ago

> it’s a much nicer ISA than anything before it (in x86 land). It's coming from Intel Knights Landing. Previous massively multicore Intel offerings used a Pentium core and had a different 512 bit SIMD instruction set, KL used a Silvermont Atom core and introduced AVX-512 and parts of it were implemented in the Skylake Purley platform in a desperate attempt to give KL more software. With little to no actual adaption and the desperate situation of being stuck on 14nm and overselling those capabilities because they expected most CPUs to move over to 10nm it was no surprise the Knights... chips got the axe. But, the insanity of AVX-512 having an entire menu of possible instruction subsets stayed.

zwegner 7y ago
Note that the 512-bit Larrabee instructions (on Knight's Ferry/Corner) had different encodings (and IIRC different encodings between KNF and KNC), but it was essentially the same instruction set. The few differences there were between LRBNI and AVX-512 had (AFAIK) almost nothing to do with the move from the old Pentium in-order core to Silvermont. I think it's also safe to assume that, given the lead time to design an ISA and integrate it into an architecture (many years), the merging of AVX-512 into Skylake wasn't done "in a desperate attempt to give KL more software". These slides from Tom Forsyth provide lots of interesting background on the evolution of the instructions: http://tomforsyth1000.github.io/papers/LRBNI%20origins%20v4%20full%20fat.pdf http://tomforsyth1000.github.io/papers/LRBNI%20origins%20v4%...

Nyan 7y ago

> I would almost prefer a more predictable, high-latency decomposition into 4x128 wide uops over what we have now. AVX512-VL gives the programmer AVX512 functionality at 128/256-bit widths, if it is believed to be more beneficial than a frequency hit.