Verilog isn't really very c-like. It is slightly more c-like than jts main competitor, VHDL. It is more c-like than lisp. But really, neither of those is say

Verilog isn't really very c-like. It is slightly more c-like than jts main competitor, VHDL. It is more c-like than lisp. But really, neither of those is saying much. Ways it is not c-like: - begin...end instead of curly braces - parallelism with assign, always, initial - tasks and functions and their subtle differences - non-blocking assignment - bit-oriented variables and operations - 4-state logic (0, 1, X, Z) - other constructs for modeling hardware like time delays, tri-state wires, drive strengths, etc. Not to mention that SystemVerilog has taken over Verilog and adds OOP with classes, a complicated (sorry, powerful) assertion mini-language, constrained randomization, a streaming operator, and so on.