> There is one exception though, and that is floating point code. I wish I had read to the end before replying (and then deleting) responses to each of your it

> There is one exception though, and that is floating point code. I wish I had read to the end before replying (and then deleting) responses to each of your items. :-) I think we're mostly in agreement, except for the following minor tidbits: > The width of the VLIW is baked into the ISA [...] no way one could even have space for that many instructions in a bundle. My understanding was that your software/compiler could indicate as many instructions as possible in parallel, and then stuff a "stop" into the 5 bit "template" to indicate the previous batch needed to commit before proceeding. So, you wouldn't be limited to 3 instructions per bundle, and if done well (hopefull), your software would automatically run faster as the next generation comes out and has more parallel execution units. > all those wasted slots in VLIW words and huge 6-bit register indices take up a lot of space in instruction encodings 128 registers, so I'd think it'd be 7 bit indices. Each instruction was 41 bits, which is roughly 5 bytes. Most SSE/AVX instructions end up being 4-5 bytes (assuming no immediates or displacements), and that's for just 4 bit register indices. So it doesn't seem much worse than we have now.