3 ms·
Do they share a memory bus? How do they contend with devices? Can an interrupt or memory access on the M7 core cause the M4 core to miss a critical timing? If s
by jschwartzi 7y ago
Do they share a memory bus? How do they contend with devices? Can an interrupt or memory access on the M7 core cause the M4 core to miss a critical timing? If so it's not really a good design.
If it's two totally independent cores with totally independent sets of devices, how do you manage the pinmux? Are there independent pinmuxes?
And finally is the M4 core capable of detecting single-faults in the cache, memory, flash registers, and instruction pipeline? Such as might be caused by cosmic rays?
These are some things I would look for if I was specifying a processor pair for use in a safety-critical system.
- magicalhippo 7y agoI tried reading the datasheet and they could have spelled out a lot of these things a bit more clearly I think. As far as I can see they have mostly separate memory busses, and a lot of the peripherals can only be accessed directly by either the M7 or the M4. Though there is some cross-bus access and how that works I have no idea. They specify that all the SRAM memory and Flash uses ECC, but no mention of the registers that I could spot. By no means a simple chip to wrap ones head around, but certainly looks interesting. Pricing of the Arduino though... not for me, at that price I'd rather take the RPi plus some extension board.