Zen 2 (except APUs) platforms went back to a separate northbridge with the memory controller not on the same piece of silicon. With the speed of current SMP in

Zen 2 (except APUs) platforms went back to a separate northbridge with the memory controller not on the same piece of silicon. With the speed of current SMP interconnects, making the chipset completely off-package again is possible, but I don't see the interest.