That is a really good idea. Sadly, RISC-V is an ultra ultra conservative design bereft, nay avoiding anything resembling an idea. I believe that an element of

That is a really good idea. Sadly, RISC-V is an ultra ultra conservative design bereft, nay avoiding anything resembling an idea. I believe that an element of your idea is done in modern x86 microarchitectures. I was having an argument on LLVMdev about a peephole optimization and partial register update stalls. Eventually one of the Intel compiler people popped in on the thread and settled the argument, saying: Regarding the partial EFLAGS write, modern OOO processors independently rename the carry flag, et al, so this is no longer a problem.