3 ms·
> #StoreRelease memory barrier even on Intel What is that? x86 is TSO... Do you have an example of the full acquire and release sections in x86 assembly?
by temac 7y ago
> #StoreRelease memory barrier even on Intel
What is that? x86 is TSO...
Do you have an example of the full acquire and release sections in x86 assembly?
- gpderetta 7y agoI'm sorry, I meant #StoreLoad. Edit: here is a good (but long) article with a x86 Peterson Lock example (with an analysis of the critical race without the barrier): https://bartoszmilewski.com/2008/11/05/who-ordered-memory-fences-on-an-x86/ https://bartoszmilewski.com/2008/11/05/who-ordered-memory-fe...