> good luck programming this insane design with anything other than a high level language compiler. That's been the RISC idea from day one. CISC ISAs were nice

> good luck programming this insane design with anything other than a high level language compiler. That's been the RISC idea from day one. CISC ISAs were nice to the assembly programmer, RISC ISAs were nice to the C programmer and the hardware implementer. Do you know how to do integer multiplication on the MIPS? I'll tell you: li $a0, 5 li $a1, 6 mult $a0, $a1 ... do some other stuff here ... mfhi $a2 mflo $v0 Why do you want to do other stuff? What's that mfhi and mflo stuff? Why is mult not three-operand? Because RISC! The MIPS model is so RISCy it exposes the fact its multiplication isn't single-cycle. It does this by making it somewhat asynchronous: You issue the multiplication opcode, and your code continues to run while the arithmetic is performed. If you try to get the result immediately, you'll stall the pipeline, so you were encouraged to schedule opcodes that don't rely on the result of the multiplication to run in that hazard. In a CISC chip, that would have been handled by microcode, and you would have gotten nice three-operand multiplication opcodes which could even do memory-to-memory operations, like on the VAX. In a RISC chip, the compiler was assumed to have all the intelligence the microcode used to have, so you got simpler-and-supposedly-faster hardware with really funky assembly language behavior. https://devblogs.microsoft.com/oldnewthing/20180404-00/?p=98435 https://devblogs.microsoft.com/oldnewthing/20180404-00/?p=98... TL;DR: Compared to the MIPS, RISC-V is a model of rationality and clarity.