4 ms·

That's main problem of RISC-V ISA: doing multi-precision arithmetic needs to do branching. It is not only a programming complexity issue, it is then very diffic

by sligor 7y ago

That's main problem of RISC-V ISA: doing multi-precision arithmetic needs to do branching. It is not only a programming complexity issue, it is then very difficult to do large number arithmetic in constant-time due to the branch predictors of modern CPUs. This can create timing-attacks problems (side-channel attacks) in algorithms like RSA. But that's the only big issue, saying that the whole ISA is insane due to this specific point of design is totally overstated

rwmj 7y ago
And also if it's important to someone to fix this, then extensions will be proposed for multi-precision arithmetic and constant time crypto primitives. RISC-V is an extensible architecture for this very reason.
justincormack 7y ago
I don't think you need branches, you can just add in the output of the correct lte (which returns 0 or 1) as the extra carry in.
- Annatar 7y ago
  Was that even English? You know processors aren't supposed to be this difficult that your skull explodes, correct?
  - Taniwha 7y ago
    doesn't matter if the compiler understands it
  - rstuart4133 7y ago
    Perhaps not normal English. But to those of us who have written a lot of assembler is was plain enough. Every heard two medical doctors discuss a patient? It's the same phenomenon. Every processor architecture (and computer language for that matter) has it's own idiosyncrasies, every assembler programmer builds up a repertoire of sequences for handling them over time. It was plain he was giving you one of those sequences, and it is pretty obvious how to apply it. Oh, and to answer your question: being simple to understand is _not_ a design criterion for processors. We've been there, done that with the VAX and later the iAPX32. It wasn't a success. We've since settled on what they are supposed to be: efficient in terms of silicon and power consumption. Architectures that win those races will be here in the long term. The VAX and iAPX32 were poor at it, and died. x86 is grimly holding onto it's niche, but I don't expect that to last. It has already lost the consumer market as most consumers use ARM now.

by sligor 7y ago

rwmj 7y ago

And also if it's important to someone to fix this, then extensions will be proposed for multi-precision arithmetic and constant time crypto primitives. RISC-V is an extensible architecture for this very reason.

justincormack 7y ago

I don't think you need branches, you can just add in the output of the correct lte (which returns 0 or 1) as the extra carry in.

Annatar 7y ago
Was that even English? You know processors aren't supposed to be this difficult that your skull explodes, correct?
- Taniwha 7y ago
  doesn't matter if the compiler understands it
- rstuart4133 7y ago
  Perhaps not normal English. But to those of us who have written a lot of assembler is was plain enough. Every heard two medical doctors discuss a patient? It's the same phenomenon. Every processor architecture (and computer language for that matter) has it's own idiosyncrasies, every assembler programmer builds up a repertoire of sequences for handling them over time. It was plain he was giving you one of those sequences, and it is pretty obvious how to apply it. Oh, and to answer your question: being simple to understand is _not_ a design criterion for processors. We've been there, done that with the VAX and later the iAPX32. It wasn't a success. We've since settled on what they are supposed to be: efficient in terms of silicon and power consumption. Architectures that win those races will be here in the long term. The VAX and iAPX32 were poor at it, and died. x86 is grimly holding onto it's niche, but I don't expect that to last. It has already lost the consumer market as most consumers use ARM now.