2 ms·

Generally, the "reduced instruction set" in RISC refers to how many instructions are available to the programmer, i.e. not many, rather than the larger number o

Generally, the "reduced instruction set" in RISC refers to how many instructions are available to the programmer, i.e. not many, rather than the larger number of instructions it then takes to accomplish anything. And the difficulty isn't really about exposing the internals, this isn't like a branch delay slot for instance. It's about making the relationship between instructions conceptually simple where there's always up to 2 inputs and up to one output. That doesn't help much in cases where the processor is doing something close to what the instructions are saying but it makes the simplest possible out of order processor, where the internals diverge wildly from the ISA, much easier to create. EDIT: Also, the using C and compiling rather than doing assembly by hand is really a fundamental part of the whole RISC philosophy and RISC-V is just a more extreme form of that.

msla 7y ago
The Reduced means that the instructions themselves are reduced, as in easier to implement and easier to implement in a pipelined implementation. As opposed to having instructions with plenty of addressing modes, you have a lot of register-register instructions and load and store opcodes: You compute the addresses explicitly, using the register-register opcodes, then load from that address using a load opcode which doesn't do much ALU work, then work on the loaded value in the registers. Contrast this with a leading CISC design, the VAX, which had plenty of addressing modes which practically all opcodes could use. A single opcode could expand into a whole stream of micro-operations to compute the addresses being loaded from, actually perform the named opcode, and then compute the address being stored to, and possibly more. Doing that in the presence of virtual memory, where an opcode might have to be stopped and restarted so the OS could take a page fault, was rather nontrivial. https://link.springer.com/chapter/10.1007%2F0-387-27446-4_3 https://link.springer.com/chapter/10.1007%2F0-387-27446-4_3

msla 7y ago

The Reduced means that the instructions themselves are reduced, as in easier to implement and easier to implement in a pipelined implementation. As opposed to having instructions with plenty of addressing modes, you have a lot of register-register instructions and load and store opcodes: You compute the addresses explicitly, using the register-register opcodes, then load from that address using a load opcode which doesn't do much ALU work, then work on the loaded value in the registers. Contrast this with a leading CISC design, the VAX, which had plenty of addressing modes which practically all opcodes could use. A single opcode could expand into a whole stream of micro-operations to compute the addresses being loaded from, actually perform the named opcode, and then compute the address being stored to, and possibly more. Doing that in the presence of virtual memory, where an opcode might have to be stopped and restarted so the OS could take a page fault, was rather nontrivial. https://link.springer.com/chapter/10.1007%2F0-387-27446-4_3 https://link.springer.com/chapter/10.1007%2F0-387-27446-4_3