3 ms·

You're saying that you want an isa where a branch is done something like Cmp rx ry rz # compare rx ry, write result to rz Jmple rz, ra, imm # jump +- ra+imm i

• ncmncm 7y ago
  No. That is close to what existing chips do. r31 = (rx<=ry)? ~0:0 (or <, etc.), result in r31 implicitly. Followed by pc = r31? pc + n : pc i.e. a single conditional branch instruction, for all conditions; or rx &= r31 effectively a conditional move instruction, or rx -= r31 effectively a conditional increment. I.e., actually reduced, but more powerful. (Implicit destination followed by mov is free, because of register renaming.) Decoding the RISC-V compare-and-branch instruction is a whole project.
  • Taniwha 7y ago
    9 lines of verilog in my decoder, 3 more in the branch unit - about the same as for, say jalr, or add immediate
  • avianes 7y ago
    > (Implicit destination followed by mov is free, because of register renaming.) There is no need for an implicit destination register, just do it explicitly and you get the same result but without any magic and with more control. Register renaming can do the same job with an implicit or explicit register destination, there is no incidence on register dependencies. > r31 = (rx<=ry)? ~0:0 Reading your first post I know that you want to use 0 and ~0 instead of the traditional 0 and 1 as the result of condition statements. I don't think that's a particularly great idea because: - there are so many places where you need 1 instead of ~0; - translating 1 into ~0 only costs one "SUB" instruction. If this feature is required for a specific domain, it's sufficient to add an extension with this feature or - more drastically - to add a macro-operation fusion step to detect this pattern. > Decoding the RISC-V compare-and-branch instruction is a whole project. RISC-V encoding is made to keep decoding as simple as possible. Have you ever checked the RISC-V encoding? It looks a bit confusing at the beginning to a human but if you think about the implementation, it immediately becomes clear. In RISC-V ISA, we can criticize: the absence of a standard SIMD extension (with a big abstract vector extension instead) or the fact that some extensions require 3 read ports on the register bank instead of 2, which can make the implementation more complex. But it's trade-offs
    • ncmncm 7y ago
      Where do you ever need 1 instead of -1? If you are using it to increment something, -1 is just as good. Storing a bool value in memory is rarely done, vs. using and discarding it. But in use, having a value to AND with, without need to dink around first, makes a big difference, particularly when cmov instructions are lacking. If the cost of negating before storing got to seem excessive, a single negate-and-store-word instruction could translate, but it would be used a very great deal less than negating the 1 to make a mask. However simple it looks to decode the thicket of compare-and-branch instructions, decoding and executing exactly one conditional branch instruction that just checks for zero will be simpler and faster. You still have the SET family to decode, but you need them anyway.