4 ms·
> The condition codes from comparison operations have always been a problem for out-of-order execution units. RISC-V doesn't have condition codes. > The extra
by thethirdone 7y ago
> The condition codes from comparison operations have always been a problem for out-of-order execution units.
RISC-V doesn't have condition codes.
> The extra step to get a comparison result into a register, and another to extend it to the whole register, is an inefficiency I would prefer to leave behind.
Can you provide RISC-V assembly that demonstrates this problem? Common branching patterns in RISC-V are all a single instruction.
The core branching comparison instructions:
`a >= b` maps to `bge a, b, label`
`a = b` maps to `beq a, b, label`
`a != b` maps to `bne a, b, label`
`a < b` maps to `blt a, b, label`
Comparisons with 0 just use the x0 register and for <= and > just flip the order of the operands.
- ncmncm 7y agoI know it does not have condition codes. Instead, it has a mess of very complex compare-and-branch instructions.
- Taniwha 7y agoIt has exactly 6 = != < >= and signed < >= - hardly "a mess" or particularly "complex"
- ncmncm 7y agoThese do not seem, to you, complex instructions? I boggle.
- pjc50 7y agoPretty much all architectures have those as a natural consequence of the way 2's complement arithmetic works? Even the tiny 6502 spends eight of its 256 opcodes on eight different branch-if-comparison opcodes.
- ncmncm 7y agoThe RISC-V compare-and-branch instructions are objectively a great deal more complex than the 6502 instructions.
- Taniwha 7y agoNo, compare and branch is kind of the expected instruction in an architecture that has no condition codes (mips has compare with 0 but essentially the same 6) - compare works well in an out of order pipe If I was going to change anything I'd add compare eq/ne with an immediate
- Annatar 7y agoThat is insane.