3 ms·
I wrote an educational simulator for RISC-V [0] two and a half years ago and the documentation for RISC-V has gotten marginally better. There a fair number of u
by thethirdone 7y ago
I wrote an educational simulator for RISC-V [0] two and a half years ago and the documentation for RISC-V has gotten marginally better. There a fair number of universities using RISC-V to teach that have published their slides and such publicly [1]. However those is not super helpful for people who already understand assembly and computer architecture reasonably well. The best way I can see to get up to speed is to read some example demonstrating each instruction. I have thought about a site that has a table of instructions that links to an online simulator [2] to let you step through an example detailing edge cases.
The best source of simple assembly examples I know of would be the tests from my project [3]. Though those could be a lot more helpful for a human reading them.
As for simulators, there are quite a few. The website lists a bunch [4]. I am not sure how many would support any kind of machine mode memory mapping though.
[0]: https://github.com/TheThirdOne/rars https://github.com/TheThirdOne/rars
[1]: https://github.com/riscv/riscv-teach https://github.com/riscv/riscv-teach
[2]: https://venus.cs61c.org/ https://venus.cs61c.org/
[3]: https://github.com/TheThirdOne/rars/tree/696ef9ed82285f0a73d80370c18be5524e95f0db/test https://github.com/TheThirdOne/rars/tree/696ef9ed82285f0a73d...
[4]: https://riscv.org/software-status/ https://riscv.org/software-status/