At the really small geometry sizes (beyond 28nm for most foundries) transistor topology has changed from planar to finfet or even variants of gate-all-around fo

At the really small geometry sizes (beyond 28nm for most foundries) transistor topology has changed from planar to finfet or even variants of gate-all-around for the really leading edge stuff. These topologies limit the leakage paths, so even at the most advanced nodes the critical issue continues to be active switching power; not to say you can just ignore leakage, but active power is and remains the dominant contributor to IR drop for CMOS semiconductor designs.