3 ms·

What material are you planning to use for cooling? We already have the power density of a nuclear reactor on some chips.

• baybal2 7y ago
  The thing is, at really small gate sizes, everything will leak so badly, that leaks will be bigger than power spent on switching the CMOS couple. And there is nothing you can do about that. That's fundamental physics. Yes, you can bury everything in HfO or a better insulator, but even that will not change the situation more than it does now. Most current coupled logic families needs less transistors, and do have higher performance than CMOS. And obviously, for as long you deal with current, noise is much less of a concern. If you cab do more computations with fewer, and higher performance transistors, that a definite win for power efficiency.
  • jgeada 7y ago
    At the really small geometry sizes (beyond 28nm for most foundries) transistor topology has changed from planar to finfet or even variants of gate-all-around for the really leading edge stuff. These topologies limit the leakage paths, so even at the most advanced nodes the critical issue continues to be active switching power; not to say you can just ignore leakage, but active power is and remains the dominant contributor to IR drop for CMOS semiconductor designs.