An actual speculation barrier (SB) instruction was added in later releases of ARMv8.0: - https://cpu.fyi/d/047#G6.11222648 https://cpu.fyi/d/047#G6.11222648 -

An actual speculation barrier (SB) instruction was added in later releases of ARMv8.0: - https://cpu.fyi/d/047#G6.11222648 https://cpu.fyi/d/047#G6.11222648 - https://cpu.fyi/d/047#E9.CHDHDDBE https://cpu.fyi/d/047#E9.CHDHDDBE along with the Consumption of Speculative Data Barrier (CSDB): https://cpu.fyi/d/047#G9.10257993 https://cpu.fyi/d/047#G9.10257993 But, as noted elsewhere in this thread, the canonical choice in most systems is DSB/ISB. Just one or the other isn't sufficient because they synchronize different things. The canonical barriers on other platforms are LFENCE (x86) and SYNC (PowerPC). For more references, see: - https://github.com/google/safeside/blob/5fb6f00f/demos/asm/measurereadlatency_x86_64.S#L31 https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m... - https://github.com/google/safeside/blob/5fb6f00f/demos/asm/measurereadlatency_ppc64le.S#L22 https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m... - https://github.com/google/safeside/blob/5fb6f00f/demos/asm/measurereadlatency_aarch64.S#L22 https://github.com/google/safeside/blob/5fb6f00f/demos/asm/m... [disclosure: I work on the Safeside project and wrote cpu.fyi as a side project]