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People were dubious of 7nm back in 2005 because back then we had '90nm' devices where the 90nm referred to the gate width. Due to the fact that making a 7nm ga
by osamagirl69 7y ago
People were dubious of 7nm back in 2005 because back then we had '90nm' devices where the 90nm referred to the gate width.
Due to the fact that making a 7nm gate width is not only impractical (even the most advanced EUV lithography can't do it) but also would make the transistors work terribly--the fact that everyone form 2005 was referring to--the industry was forced to innovate. Their clever solution was to change their naming convention, and instead of naming each technology node after the actual gate width they just assign them a arbitrary number which follows moores law. [1]
The actual gate width for a '7nm' process is somewhat ill defined (they look nothing like a textbook transistor), but depending on how you measure it the number comes in somewhere between 30-60nm. [2] Note that there is a number in the 7nm dimensional chart that comes in at 6nm, but that is the gate oxide thickness, and is actually getting _thicker_ over time. For example back in 90nm it was 1-2nm thick.
That said, those skeptical of us ever producing a '7nm' transistor back in 2005 were right--by the naming convention used in 2005 we are still at ~40nm. I am sure that you will be able to buy a '2nm' processor according to the roadmap, but the actual transistors are still going to have a gate width closer to 30nm and their electrical performance is going to be within a factor of 2 of our current '7nm', and honestly probably going to be clocked slower.
[1] https://en.wikichip.org/wiki/technology_node https://en.wikichip.org/wiki/technology_node
[2] https://en.wikichip.org/wiki/7_nm_lithography_process https://en.wikichip.org/wiki/7_nm_lithography_process
- agumonkey 7y agoI think I've read some knowledgeable silicon guy saying he wouldn't bet a dime on 7nm quite a time after 2005 (2012~). But I forgot the details.
- kllrnohj 7y agoMeasuring gate width also stopped being relevant. Densities continue to increase, and significantly so, despite gate-width staying relatively constant. A 45nm process: i7-880, 45nm 774 million transistors 296 mm2 A "14nm" process: i7-6700k, 14nm 1.75 billion transistors 122 mm² That's still a huge increase in density. It no longer means what it used to, but the spirit of the definition is still very much alive.
- osamagirl69 7y agoIt is a significant increase in density, but falls well short of the expectation. Density is somewhat hard to compare because it depends on the way the chip is laid out and the amount of cache vs logic, but if we go by the size of a single sram cell (containing 4 transistors) we can make a relatively fair comparison. In 90nm a sram cell was 1um^2 and in 7nm a ram cell is .027um^2, an increase in density of 37x. The expected scaling is that transistor density should have scaled with gate length squared (since the structures are laid out in a 2-D grid, for example the 0.8um process used in the 8088 had a sram density of 120um^2, compared to 1um^2 squared for 90nm, a factor of 120x for a roughly 10 times smaller process), so one would have expected a 165x improvement moving from 90nm to 7nm. Unsurprisingly, the missing factor of 5 is the same factor between the process node name ('7nm') and actual gate length (~35nm).