4 ms·

> Seems like Cray had several 64*64 = 4096 bit vector register, but you worked on it only 64 bit at a time What makes you say that? There seem to be the usual

> Seems like Cray had several 64*64 = 4096 bit vector register, but you worked on it only 64 bit at a time What makes you say that? There seem to be the usual vector-vector instructions: 161ijk Vi Vj+Vk > Are those Intel vector register sizes going to increase I don't see how they could. The vector size has increased from XMM to YMM to ZMM, there is obviously no more room for expansion ;-)

jabl 7y ago
> > but you worked on it only 64 bit at a time > What makes you say that? Ye olde Crays used 'vector pipelining', meaning that while vector registers held many elements, there was only one ALU. So a single vector instruction took many cycles to execute. OTOH this enabled the execution units to be well utilized even without a cache, heroic OoO etc.
- gpderetta 7y ago
  Yes, if I understand correctly, at the time instruction fetch/dispatch was the bottleneck, so vector instructions would keep the execution units busy with data streamed directly from main memory (there was no need for cache because, at least for throughput oriented applications, main memory was not significantly slower than the cpu itself).
  - jabl 7y ago
    Also, Crays of yore used SRAM for main memory. And back then there was also much less of a gap between memory bus speed and cpu speed. This combined with the vector pipelining made caches somewhat unnecessary.
    - jtlienwis 7y ago
      Cray-2 was all dram except for maybe one of the first to ship which was sram.
- dragontamer 7y ago
  Note that last-gen AMD Vega64 GPUs would still be "vector-pipelined" across 4-clock ticks. A 64x wide logical wavefront on a Vega64 would be physically executed by a 16x wide ALU. The ALU would pipeline itself over 4-clock ticks, providing the programmer a logical 64x wide vector.
dr_zoidberg 7y ago
> I don't see how they could. The vector size has increased from XMM to YMM to ZMM, there is obviously no more room for expansion ;-) One thought comes to mind: WMM, standing for "Wider MM register" But then another one, like they've already done: EXMM, EYMM, EZMM -- as in A, AX, EAX, RAX... (captain obvious: I know it was a joke...) Edit: formatting

jabl 7y ago

> > but you worked on it only 64 bit at a time > What makes you say that? Ye olde Crays used 'vector pipelining', meaning that while vector registers held many elements, there was only one ALU. So a single vector instruction took many cycles to execute. OTOH this enabled the execution units to be well utilized even without a cache, heroic OoO etc.

gpderetta 7y ago
Yes, if I understand correctly, at the time instruction fetch/dispatch was the bottleneck, so vector instructions would keep the execution units busy with data streamed directly from main memory (there was no need for cache because, at least for throughput oriented applications, main memory was not significantly slower than the cpu itself).
- jabl 7y ago
  Also, Crays of yore used SRAM for main memory. And back then there was also much less of a gap between memory bus speed and cpu speed. This combined with the vector pipelining made caches somewhat unnecessary.
  - jtlienwis 7y ago
    Cray-2 was all dram except for maybe one of the first to ship which was sram.
dragontamer 7y ago
Note that last-gen AMD Vega64 GPUs would still be "vector-pipelined" across 4-clock ticks. A 64x wide logical wavefront on a Vega64 would be physically executed by a 16x wide ALU. The ALU would pipeline itself over 4-clock ticks, providing the programmer a logical 64x wide vector.

dr_zoidberg 7y ago

> I don't see how they could. The vector size has increased from XMM to YMM to ZMM, there is obviously no more room for expansion ;-) One thought comes to mind: WMM, standing for "Wider MM register" But then another one, like they've already done: EXMM, EYMM, EZMM -- as in A, AX, EAX, RAX... (captain obvious: I know it was a joke...) Edit: formatting