Transport Triggered Architecture seems not only isomorphic but essentially equivalent to a conventional architecture if you notice it is effectively just reloca

Transport Triggered Architecture seems not only isomorphic but essentially equivalent to a conventional architecture if you notice it is effectively just relocating/packing the opcode bits into the operands. This seems to be an implementation detail of the hardware (which bits does it gather opcodes from) and not an essential difference in the ISA. Am I missing something?