9 ms·

Aw, I was hoping the explanation would be in the thread. Is it high-frequency noise from an unshielded clock? Surpassing a current or temperature limit due to t

Aw, I was hoping the explanation would be in the thread. Is it high-frequency noise from an unshielded clock? Surpassing a current or temperature limit due to the stress of the high resolution and resulting high memory bandwidth? Time will tell!

duskwuff 7y ago
> Is it high-frequency noise from an unshielded clock? I bet that's it. 2560x1440 @ 60 Hz with CVT-RB timings has a pixel clock of 241.5 MHz. The TMDS bit rate is 10x the pixel clock, and 2415 MHz is right in the lower end of the 802.11 band. If the Pi can be convinced to use CVT blanking, that'll raise the pixel clock to 312 MHz, which should be fine.
- amaterasu 7y ago
  And unlike hdmi 2.0, 1.4 wont have scrambling in, so any termination issues will sing quite well.
  - wolfgke 7y ago
    > And unlike hdmi 2.0, 1.4 wont have scrambling in, so any termination issues will sing quite well. Not an electrical engineer: which measures are usually adapted to handle termination issues?
    - willis936 7y ago
      Moar power, isolation, and voltage regulators.
      - HeWhoLurksLate 7y ago
        And grounding!
- Akababa 7y ago
  I so badly want this to be true - it's like a perfectly designed bug!
- Zobat 7y ago
  Not the numbers the calculator I found online came up with, but I had the same thought. I'm thinking that changing the refresh rate could solve the problem.
  - duskwuff 7y ago
    The calculator I was using was: https://tomverbeure.github.io/video_timings_calculator https://tomverbeure.github.io/video_timings_calculator Changing the refresh rate would work too, but some monitors can be pretty picky about that.
- archi42 7y ago
  I thought something similar: Pixel clock or some harmonic of it feeding back into the wifi chip via the power lines (image search says the chip is in a metal box, so should not be via over-the-air-RF). Thanks for doing the math. Forcing a different pixel clock is probably the easiest fix, and since the ports claim to do 4kp60, that should be possible (if the display supports it).
- marcan_42 7y ago
  This is the answer. That mode puts the second harmonic going out of the HDMI cable smack in the 2.4GHz WiFi band (the fundamental would be at 1/2 the bit rate). Now the question is who screwed up. Is it a leaky cable? Is it bad PCB design? Is it a problem internal to the SoC? Is it a power delivery issue? Knowing the RPi foundation and Broadcom, I bet one of them screwed this up for all RPis and it isn't just a bad cable.
  - walterman 7y ago
    I'm trying to understand this so I don't know a lot of what's going on here, but why is the fundamental half the bit rate instead of the bit rate?
    - wrigby 7y ago
      I'm not 100% sure, but I'm assuming because of Double Data Rate transfers: https://en.wikipedia.org/wiki/Double_data_rate https://en.wikipedia.org/wiki/Double_data_rate
    - duskwuff 7y ago
      Imagine a signal that alternates every second (e.g. 10101010). This has a frequency of 1/2 Hz, not 1 Hz, because it repeats every 2 seconds.
- deleted 7y ago
  [deleted]
- anthk 7y ago
  That reminds me of this: https://bellard.org/dvbt/ https://bellard.org/dvbt/

duskwuff 7y ago

> Is it high-frequency noise from an unshielded clock? I bet that's it. 2560x1440 @ 60 Hz with CVT-RB timings has a pixel clock of 241.5 MHz. The TMDS bit rate is 10x the pixel clock, and 2415 MHz is right in the lower end of the 802.11 band. If the Pi can be convinced to use CVT blanking, that'll raise the pixel clock to 312 MHz, which should be fine.

amaterasu 7y ago
And unlike hdmi 2.0, 1.4 wont have scrambling in, so any termination issues will sing quite well.
- wolfgke 7y ago
  > And unlike hdmi 2.0, 1.4 wont have scrambling in, so any termination issues will sing quite well. Not an electrical engineer: which measures are usually adapted to handle termination issues?
  - willis936 7y ago
    Moar power, isolation, and voltage regulators.
    - HeWhoLurksLate 7y ago
      And grounding!
Akababa 7y ago
I so badly want this to be true - it's like a perfectly designed bug!
Zobat 7y ago
Not the numbers the calculator I found online came up with, but I had the same thought. I'm thinking that changing the refresh rate could solve the problem.
- duskwuff 7y ago
  The calculator I was using was: https://tomverbeure.github.io/video_timings_calculator https://tomverbeure.github.io/video_timings_calculator Changing the refresh rate would work too, but some monitors can be pretty picky about that.
archi42 7y ago
I thought something similar: Pixel clock or some harmonic of it feeding back into the wifi chip via the power lines (image search says the chip is in a metal box, so should not be via over-the-air-RF). Thanks for doing the math. Forcing a different pixel clock is probably the easiest fix, and since the ports claim to do 4kp60, that should be possible (if the display supports it).
marcan_42 7y ago
This is the answer. That mode puts the second harmonic going out of the HDMI cable smack in the 2.4GHz WiFi band (the fundamental would be at 1/2 the bit rate). Now the question is who screwed up. Is it a leaky cable? Is it bad PCB design? Is it a problem internal to the SoC? Is it a power delivery issue? Knowing the RPi foundation and Broadcom, I bet one of them screwed this up for all RPis and it isn't just a bad cable.
- walterman 7y ago
  I'm trying to understand this so I don't know a lot of what's going on here, but why is the fundamental half the bit rate instead of the bit rate?
  - wrigby 7y ago
    I'm not 100% sure, but I'm assuming because of Double Data Rate transfers: https://en.wikipedia.org/wiki/Double_data_rate https://en.wikipedia.org/wiki/Double_data_rate
  - duskwuff 7y ago
    Imagine a signal that alternates every second (e.g. 10101010). This has a frequency of 1/2 Hz, not 1 Hz, because it repeats every 2 seconds.
deleted 7y ago
[deleted]
anthk 7y ago
That reminds me of this: https://bellard.org/dvbt/ https://bellard.org/dvbt/