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EDA tools are a different beast... There is a reason why the field is completely monopolized by the big three - Cadence, Synopsys, and Mentor Graphics. And a l

by Cyph0n 7y ago

EDA tools are a different beast... There is a reason why the field is completely monopolized by the big three - Cadence, Synopsys, and Mentor Graphics. And a lot of the tools you mentioned are targeted towards FPGA design rather than full or semi-custom ASIC design. The big three have tools that can handle both.

paulgerhardt 7y ago
Let’s not get ahead of ourselves. Relative to something like Microsoft Office they’re tiny and we have open competitive solutions there (a product notorious for a billion corner cases). And let’s not forget “EDA software” was single handedly pioneered by one woman and some lisp. Before then, it was hundreds of men taping out circuits on 4x8’ ply with...physical tape who all complained the labor and complexity costs were enormous and nothing could be done. If we really want to point fingers, we could say it’s a monopoly on the supply chain side of manufacturing - costing millions in NRE’s to make a chip - but if you are willing to scrimp on process size you can get it done for $3 per layer per reticle at 500nm scale and $50 per mask.
- choudanu4 7y ago
  Since you seem to know, what company would one go to for fabricating a 500nm chip these days at that price?
  - JetSpiegel 7y ago
    500nm feature size is positively ancient. Any of the myriad fabless companies won't even care about those dinosaur technologies. I would try the local university with an electronics program.
- therealcamino 7y ago
  To make things more concrete than "big" or "relatively...tiny", some quick googling puts Cadence's annual R&D spending at a little less than $1B and Synopsys's around $1.2B. Mentor Graphics is part of Siemens, so that'd be harder to figure out.
  - Cyph0n 7y ago
    It’s a strawman. I never used “big” in an absolute sense, so it’s implied that I meant “big” in their field.
- Cyph0n 7y ago
  Are you seriously trying to compare document processors to state of the art EDA tools?

by Cyph0n 7y ago

paulgerhardt 7y ago

Let’s not get ahead of ourselves. Relative to something like Microsoft Office they’re tiny and we have open competitive solutions there (a product notorious for a billion corner cases). And let’s not forget “EDA software” was single handedly pioneered by one woman and some lisp. Before then, it was hundreds of men taping out circuits on 4x8’ ply with...physical tape who all complained the labor and complexity costs were enormous and nothing could be done. If we really want to point fingers, we could say it’s a monopoly on the supply chain side of manufacturing - costing millions in NRE’s to make a chip - but if you are willing to scrimp on process size you can get it done for $3 per layer per reticle at 500nm scale and $50 per mask.

choudanu4 7y ago
Since you seem to know, what company would one go to for fabricating a 500nm chip these days at that price?
- JetSpiegel 7y ago
  500nm feature size is positively ancient. Any of the myriad fabless companies won't even care about those dinosaur technologies. I would try the local university with an electronics program.
therealcamino 7y ago
To make things more concrete than "big" or "relatively...tiny", some quick googling puts Cadence's annual R&D spending at a little less than $1B and Synopsys's around $1.2B. Mentor Graphics is part of Siemens, so that'd be harder to figure out.
- Cyph0n 7y ago
  It’s a strawman. I never used “big” in an absolute sense, so it’s implied that I meant “big” in their field.
Cyph0n 7y ago
Are you seriously trying to compare document processors to state of the art EDA tools?