The x86 hardware decoder on Itanium turned out to be slower than a JIT, and was removed from hardware pretty quickly. Also note that the x86 memory model is a

The x86 hardware decoder on Itanium turned out to be slower than a JIT, and was removed from hardware pretty quickly. Also note that the x86 memory model is a perfectly valid implementation for an ARM chip, as it's a superset of the ARM memory model constraints. And the performance impact isn't that big really.