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Yes there are chips that support multiple ISAs...although typically one ISA is more native. At least, I believe NVIDIA Denver qualifies as that[1]. Also I belie
by als0 7y ago
Yes there are chips that support multiple ISAs...although typically one ISA is more native. At least, I believe NVIDIA Denver qualifies as that[1]. Also I believe some Itanium chips had a (slow) x86 hardware decoder that changed the instructions into the native EPIC instruction set[2].
However, unifying the memory models sounds like a performance disaster for the ARM code. And having multiple decoders in hardware (as well as having enough of them) doesn't seem like a justifiable use of silicon real estate.
[1] https://en.wikipedia.org/wiki/Project_Denver https://en.wikipedia.org/wiki/Project_Denver
[2] https://www.techsupportalert.com/pdf/r1048.pdf https://www.techsupportalert.com/pdf/r1048.pdf
- my123 7y agoThe x86 hardware decoder on Itanium turned out to be slower than a JIT, and was removed from hardware pretty quickly. Also note that the x86 memory model is a perfectly valid implementation for an ARM chip, as it's a superset of the ARM memory model constraints. And the performance impact isn't that big really.
- als0 7y agoYes, I agree with you. Many of the barrier instructions will end up as internal NOPs. Performance wouldn't be terrible. Power may suffer.