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Where is x86-64 mentioned? I assumed they were building ARM chips. In any case, they don't mention any secret sauce. Intel has strong channels, fabs and the x8

Where is x86-64 mentioned? I assumed they were building ARM chips. In any case, they don't mention any secret sauce. Intel has strong channels, fabs and the x86-64 ISA with massive software compatibility on the server side. Even with better performance/power, Intel can simply undercut the competition to drive them out of business. If Qualcomm's sales channels couldn't dent the server space, I am sceptical about upstarts, unless their [power, performance, cost] is significantly better than Intel.

lnsru 7y ago
I was also immediately thinking about Qualcomm’s processors business. From this point of view I don’t see success for this startup: https://www.tomshardware.com/news/qualcomm-server-chip-exit-china-centriq-2400,38223.html https://www.tomshardware.com/news/qualcomm-server-chip-exit-...
chrisseaton 7y ago
Are there any chips which support multiple ISAs? Could a single chip decode both AMD64 and ARM instruction streams? Or could the memory models not be unified so it's not possible?
- als0 7y ago
  Yes there are chips that support multiple ISAs...although typically one ISA is more native. At least, I believe NVIDIA Denver qualifies as that[1]. Also I believe some Itanium chips had a (slow) x86 hardware decoder that changed the instructions into the native EPIC instruction set[2]. However, unifying the memory models sounds like a performance disaster for the ARM code. And having multiple decoders in hardware (as well as having enough of them) doesn't seem like a justifiable use of silicon real estate. [1] https://en.wikipedia.org/wiki/Project_Denver https://en.wikipedia.org/wiki/Project_Denver [2] https://www.techsupportalert.com/pdf/r1048.pdf https://www.techsupportalert.com/pdf/r1048.pdf
  - my123 7y ago
    The x86 hardware decoder on Itanium turned out to be slower than a JIT, and was removed from hardware pretty quickly. Also note that the x86 memory model is a perfectly valid implementation for an ARM chip, as it's a superset of the ARM memory model constraints. And the performance impact isn't that big really.
    - als0 7y ago
      Yes, I agree with you. Many of the barrier instructions will end up as internal NOPs. Performance wouldn't be terrible. Power may suffer.
- tyingq 7y ago
  Transmeta did this. It emulated the x86 ISA, though the actual ISA was not x86. They did a demo of it translating JVM bytecode directly to its own VLIW ISA with no x86 running at all.
  - deleted 7y ago
    [deleted]
WillSlim95 7y ago
If Jon Masters is present, it is a very high guarantee that they are focusing on ARM server chips

lnsru 7y ago

I was also immediately thinking about Qualcomm’s processors business. From this point of view I don’t see success for this startup: https://www.tomshardware.com/news/qualcomm-server-chip-exit-china-centriq-2400,38223.html https://www.tomshardware.com/news/qualcomm-server-chip-exit-...

chrisseaton 7y ago

Are there any chips which support multiple ISAs? Could a single chip decode both AMD64 and ARM instruction streams? Or could the memory models not be unified so it's not possible?

als0 7y ago
Yes there are chips that support multiple ISAs...although typically one ISA is more native. At least, I believe NVIDIA Denver qualifies as that[1]. Also I believe some Itanium chips had a (slow) x86 hardware decoder that changed the instructions into the native EPIC instruction set[2]. However, unifying the memory models sounds like a performance disaster for the ARM code. And having multiple decoders in hardware (as well as having enough of them) doesn't seem like a justifiable use of silicon real estate. [1] https://en.wikipedia.org/wiki/Project_Denver https://en.wikipedia.org/wiki/Project_Denver [2] https://www.techsupportalert.com/pdf/r1048.pdf https://www.techsupportalert.com/pdf/r1048.pdf
- my123 7y ago
  The x86 hardware decoder on Itanium turned out to be slower than a JIT, and was removed from hardware pretty quickly. Also note that the x86 memory model is a perfectly valid implementation for an ARM chip, as it's a superset of the ARM memory model constraints. And the performance impact isn't that big really.
  - als0 7y ago
    Yes, I agree with you. Many of the barrier instructions will end up as internal NOPs. Performance wouldn't be terrible. Power may suffer.
tyingq 7y ago
Transmeta did this. It emulated the x86 ISA, though the actual ISA was not x86. They did a demo of it translating JVM bytecode directly to its own VLIW ISA with no x86 running at all.
- deleted 7y ago
  [deleted]

WillSlim95 7y ago

If Jon Masters is present, it is a very high guarantee that they are focusing on ARM server chips