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To quote from https://fgiesen.wordpress.com/2014/07/07/cache-coherency/ https://fgiesen.wordpress.com/2014/07/07/cache-coherency/ "Memory models Different arc
by mrich 7y ago
To quote from https://fgiesen.wordpress.com/2014/07/07/cache-coherency/ https://fgiesen.wordpress.com/2014/07/07/cache-coherency/
"Memory models
Different architectures provide different memory models. As of this writing, ARM and POWER architecture machines have comparatively “weak” memory models: the CPU core has considerable leeway in reordering load and store operations in ways that might change the semantics of programs in a multi-core context, along with “memory barrier” instructions that can be used by the program to specify constraints: “do not reorder memory operations across this line”. By contrast, x86 comes with a quite strong memory model."
- gpderetta 7y agoYes, I know the difference between the memory model of x86 and, say, ARM. I'm asking what's x86 specific on this article about cache coherency.
- mrich 7y agoThe article explicitly mentions two times things that are only true for x86 (grep for it). In addition, the statement at the end is definitely not true for POWER: "As soon as the data is read/written to the L1 cache, the hardware-coherency protocol takes over and provides guaranteed coherency across all global threads. Thus ensuring that if multiple threads are reading/writing to the same variable, they are all kept in sync with one another."