https://www.kernel.org/doc/Documentation/memory-barriers.txt https://www.kernel.org/doc/Documentation/memory-barriers.txt has a pretty concise explanation of ac

https://www.kernel.org/doc/Documentation/memory-barriers.txt https://www.kernel.org/doc/Documentation/memory-barriers.txt has a pretty concise explanation of acquire/release. Basically core1 core2 --------- --------- acquire x write x release x acquire x read x release x guarantees that core2 will read core1's value for x, yet is less expensive than fully flushing both caches. Without the memory barriers, the write could be moved down the timeline (queued for writeback) and the read moved up (served from cache) so that core2 doesn't see what core1 wanted to write.