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For the 4000 series, they're planning on sharing the L3 caches between CCD's/ chiplets rather than per CCX. It will be interesting to see if the more cache avai

For the 4000 series, they're planning on sharing the L3 caches between CCD's/ chiplets rather than per CCX. It will be interesting to see if the more cache availible per core, and more cores being able to access the same cache will improve the performance. The speed AMD has raised caches & core-count lately is insane. When the max for mainstream CPUs was 8MB (and 4 cores) until only a few years ago. (Things seem to have stopped when quad-core launched, the Intel Q6600 was an amazing CPU at the time.) I've been a computer enthusiast for over 20 years and didn't expect to see advancements to return like the good ol' days (Moore's law) to ever return. (I don't think Intel did either, halving their prices pre-launch is unprecidented!)

gameswithgo 7y ago
Yes I look forward to the better cache system in the next generation! Do remember that part of how AMD can get so much L3 on there, is due to the chiplet design, which also adds a LOT of latency to ram accesses. Almost all of the time, it seems to be a net win though, and with the next generation it will only get better.
mjevans 7y ago
It would be interesting if we moved back to the final layer of cache being off-core, likely within the IO die or attached as additional chips within the package. That should decrease the core size, improve yields, and allow for differentiation in L3 size as well.
- gameswithgo 7y ago
  but it would add latency :( but maybe an L4 cache, off core, as additional chips!
  - paulmd 7y ago
    Interestingly, Broadwell-S and Broadwell-R did this using the "Crystal Well" L4 cache. However, DDR4 memory now provides more bandwidth than the L4 could (although probably at a higher latency).
  - wahern 7y ago
    At some point both higher latencies and deeper cache hierarchies seem inevitable: http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html Though, perhaps 3D integration can stave that off for many more generations.

gameswithgo 7y ago

Yes I look forward to the better cache system in the next generation! Do remember that part of how AMD can get so much L3 on there, is due to the chiplet design, which also adds a LOT of latency to ram accesses. Almost all of the time, it seems to be a net win though, and with the next generation it will only get better.

mjevans 7y ago

It would be interesting if we moved back to the final layer of cache being off-core, likely within the IO die or attached as additional chips within the package. That should decrease the core size, improve yields, and allow for differentiation in L3 size as well.

gameswithgo 7y ago
but it would add latency :( but maybe an L4 cache, off core, as additional chips!
- paulmd 7y ago
  Interestingly, Broadwell-S and Broadwell-R did this using the "Crystal Well" L4 cache. However, DDR4 memory now provides more bandwidth than the L4 could (although probably at a higher latency).
- wahern 7y ago
  At some point both higher latencies and deeper cache hierarchies seem inevitable: http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html Though, perhaps 3D integration can stave that off for many more generations.