Part of the driver of IPC is how many layers of logic you can fit between each pipeline register. We’re not talking density we’re talking logic gate delay. Eac

Part of the driver of IPC is how many layers of logic you can fit between each pipeline register. We’re not talking density we’re talking logic gate delay. Each process has different delay, setup, and hold times. On one process I might be able to fit 15 layers of logic before I have to add a pipeline stage. On another I might be able to fit 20 at the same frequency. Pipeline stages are also not free with each adding additional overhead. This determines how advanced I can make things like my branch predictor or cache pre-fetcher while still meeting timing requirements. For example I might want a larger lookback buffer but I can’t use a larger memory - not because of how much area it takes but because it simply takes too long to do the look up now.