I mean I'm no chip designer but surely they are using some crazy hacks like transistors that take up more space than the lines between them by being part of the

I mean I'm no chip designer but surely they are using some crazy hacks like transistors that take up more space than the lines between them by being part of the substraight above and below the etched lines. And presumably they use interference/coherence to etch even finer details? There are probably about a million different techniques they use to pack in more transistors without making the process smaller.