4 ms·
> The other TSX sub-feature, Hardware Lock Elision (HLE), is unconditionally disabled by the new microcode but still enumerated as present by CPUID(EAX=7).EBX{b
by my123 7y ago
> The other TSX sub-feature, Hardware Lock Elision (HLE), is
unconditionally disabled by the new microcode but still enumerated
as present by CPUID(EAX=7).EBX{bit4}, unless disabled by
IA32_TSX_CTRL_MSR[1] - TSX_CTRL_CPUID_CLEAR.
Disabling HLE makes the code still works because of the backward ISA compatibility... but you still lose the performance benefits of HLE.
Also, disabling it but still keeping it shown in CPUID...
- saagarjha 7y agoSo if I'm understanding this correctly, xacquire/xrelease now unconditionally fall back to being interpreted as the (useless) repne/repe prefixes, even on chips that "support" HLE?
- my123 7y agoYes...
- the-dude 7y agoIs anything know about how much performance will be lost?
- NicoJuicy 7y agohttps://twitter.com/damageboy/status/1194751035136450560?s=19 https://twitter.com/damageboy/status/1194751035136450560?s=1... Up to 20% for Array.Sort
- asveikau 7y agoWhy would Array.Sort have locking in need of elision? [I'm reminded of the old Java "Vector" or "StringBuffer" that put a lock around every operation "because thread safety is good" which had high cost for single threaded usage. But this is likely not what this is about.]
- makomk 7y agoWell, judging from the Phoronix benchmarks, performance is worse than just outright disabling TSX in its entirety: https://www.phoronix.com/scan.php?page=article&item=zombieload-v2-taa&num=1 https://www.phoronix.com/scan.php?page=article&item=zombielo... (Though they show basically no performance benefit from TSX, so...)