3 ms·
Any info on the difference of latency of register access vs. L1 cache on x86_64? When looking at compiler output of gcc most of the time it puts variables with
by sprash 7y ago
Any info on the difference of latency of register access vs. L1 cache on x86_64?
When looking at compiler output of gcc most of the time it puts variables within a scope on the stack and rarely populates all registers or even any at all. Wouldn't using the full 12-14 available first be faster?
- jcranmer 7y agoAn L1 cache hit is 4 cycles of latency. As for your second question, my guess is you're looking at unoptimized code. Most compilers keep variables on the stack unless you're optimizing the code to at least some degree.