4 ms·
I've seen this table many times and I'm always surprised it doesn't include register.
by CalChris 7y ago
I've seen this table many times and I'm always surprised it doesn't include register.
- tenebrisalietum 7y agoRegisters should have zero latency. They're literally within the same part of the CPU that decodes the instructions.
- zenmaster10665 7y agoWell zero as in one or two clock cycles?
- 8K832d7tNmiQ 7y agozero as in directly connected to its instruction set
- jcranmer 7y agoA fraction of a clock cycle. An execution unit is basically an ALU with a set of muxes for inputs, where the muxes are pulling either from the registers or from later execution stages that have yet to commit their results to registers. The entire path has to settle down by the time the clock signal reaches the latch at the edge of the stage to retain the value for the next clock cycle. This means that the time it takes to read a register is a fraction of the single clock cycles that 1-clock-cycle µops take to run.
- CalChris 7y agoRegisters are finitely faster, not infinitely faster, than L1. Now if registers were infinitely faster than L1 then that table would really want to raise that hosanna to the highest.
- yjftsjthsd-h 7y agoHow about "faster than anything interacting with them (so effectively infinite"? (I agree that calling it infinite is a little weird, although it's better if one considers that infinity is usually shorthand)