4 ms·
They get that IPC on a better process. Shorter gate delays let you pack more into each cycle. IPC can't be divorced from process when comparing architectures.
by jdsully 7y ago
They get that IPC on a better process. Shorter gate delays let you pack more into each cycle. IPC can't be divorced from process when comparing architectures.
- kllrnohj 7y agoIPC is from design not from transistor density. Clock speed is what can't be divorced from process. IPC can be. More transistors could enable new designs not previously feasible, but we've loooong since past that point (hence why most new transistors are just being dumped into L3 cache)
- jdsully 7y agoPart of the driver of IPC is how many layers of logic you can fit between each pipeline register. We’re not talking density we’re talking logic gate delay. Each process has different delay, setup, and hold times. On one process I might be able to fit 15 layers of logic before I have to add a pipeline stage. On another I might be able to fit 20 at the same frequency. Pipeline stages are also not free with each adding additional overhead. This determines how advanced I can make things like my branch predictor or cache pre-fetcher while still meeting timing requirements. For example I might want a larger lookback buffer but I can’t use a larger memory - not because of how much area it takes but because it simply takes too long to do the look up now.