4 ms·
A lot of the inefficiency of FPGAs is signal routing. If you are very likely to implement X, Y, or Z, then it may just be more economical to put those into the
by snagglegaggle 7y ago
A lot of the inefficiency of FPGAs is signal routing. If you are very likely to implement X, Y, or Z, then it may just be more economical to put those into the FPGA as discrete circuits. At best maybe you can break them apart into common elements and provide those.
There really isn't much need for LUTs any more, barring some fundamental change in data processing.
- monocasa 7y agoThat doesn't really follow given that LUT count has been increasing with Moore's law.
- snagglegaggle 7y agoI see your point, but I think that is because of a lack of commitment to higher integration functional blocks. A lot of work done on a FPGA is very regular. I suppose LUTs could be the best way to do create the glue logic that basically amounts to signal routing and synchronization, but it seems unlikely.
- dragontamer 7y agoI'm not going to be surprised if FPGAs of the future start building in on-chip non-blocking CLOS-networks to more efficiently route messages across the chip. https://en.wikipedia.org/wiki/Clos_network https://en.wikipedia.org/wiki/Clos_network Dedicated-hardware that serves a purpose. Sure, you can build a CLOS-network out of LUTs, but it'd be more efficient if you made dedicated hardware for it instead.
- monocasa 7y agoI wouldn't be surprised if some do that under the hood already. The cadence hardware emulators for sure do, but they're not quite FPGAs.
- monocasa 7y agoIf you can get by with higher level functional blocks sitting off of a network on chip, you go the direction of a modern SoC. The neat games you can play with routing those NoC packets around are close to what you're talking about.