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I wonder whether writing whole system in verilog, synthesizing cycle accurate simulator with verilator would yield better results...
by artemonster 7y ago
I wonder whether writing whole system in verilog, synthesizing cycle accurate simulator with verilator would yield better results...
- ginko 7y agoI work for a silicon IP company and the verilog simulation of our product is about a factor of ten slower than our "cycle accurate" software model. The FPGA version is about 40 times or so faster than the model and the actual silicon is another 10 times or so faster than that.
- bhouston 7y agoHow cheap are fgpas that could simulate an SNES or similar? Any chance we standardize and commoditize fpgas so that it can be just another device on a laptop or phone that anyone could use? Like bluetooth or a GPU or gps? This has to happen at some point but how far off from that are we now? I assume there are different grades of fpgas and that likely complicates things but it is like desktop GPUs are way way better than phone GPUs... But both run opengl/vulkan and essentially the same code.
- gpderetta 7y agoI know of FPGA based implementation of whole Amigas [1] and I do not htink they are particularly expensive. It is very likely that SNES reimplementations also exist already. Edit: this [2] is a full system for 220 euros and in addition to Amiga it emulates a bunch of 8 bit consoles. [1]: https://en.wikipedia.org/wiki/Minimig https://en.wikipedia.org/wiki/Minimig [2]: https://amigastore.eu/en/358-mist-midi-fpga-computer-with-midi-add-on.html https://amigastore.eu/en/358-mist-midi-fpga-computer-with-mi...
- krupan 7y agoThose are very good questions. I have a feeling that Intel is looking into this now that they have purchased Altera.
- byuu 7y agoVerilog lets you model things natively in parallel, but few people have user-programmable FPGAs lying around sadly. Very cool tech, though!
- krupan 7y agoJust to be clear, artemonster isn't talking about using an FPGA. Verilator is software that complies Verilog to C++, so you'd still end up with a software emulator. The upside to this is that Verilog makes it very easy to model parallel hardware. The downside is that you have to model the hardware at the clock-cycle, "flip-flops and Boolean logic" level of detail.
- krupan 7y agoLike ginko says, it probably wouldn't. Verilator still requires you to model at a very low level (sythesizable RTL), much lower than this article is describing. That detailed of a model is going to be slower than what you can do without that restriction. Now, that's not to say that it wouldn't be good enough, i.e., fast enough that your games would still be playable. It's an interesting idea.