3 ms·
Multiple Mellanox or Chelsio 100GbE NICs in an LACP bundle. The 220g is from a prototype with a Rome CPU in a Naples-designed motherboard, with 4 Mellanox Conn
by drewg123 7y ago
Multiple Mellanox or Chelsio 100GbE NICs in an LACP bundle.
The 220g is from a prototype with a Rome CPU in a Naples-designed motherboard, with 4 Mellanox ConnectX-4 100GbE NICs. 2 of them are limited to Gen 3 x8 (since it is a Naples generation mobo).
- Teknoman117 7y agoI'm curious about you being limited to 220 Gb/s on an AMD Rome box. The maximum theoretical DDR4 bandwidth on such a system with 3200 MT DDR4 is 204 GiB/s, so you'd only be using ~15% of the DRAM bandwidth assuming the block/record/file size of the cached data you're serving is enough to mask the DRAM latency.