4 ms·

In-memory database acceleration on FPGAs: a survey

87 points by matt_d 7y ago

xiaodai 7y ago
The DPU (Data Processing Unit) which is specialist unit like the GPU but for data tasks like sorting, grouping will be a reality soon!
- lmeyerov 7y ago
  It's a tough space.. seems more economically feasible to just slightly update GPUs for it, similar to what's happening for ML/tensors/etc, and for the rest, FPGAs for prototyping => ASICs for deployment. We were originally building on OpenCL to keep this path open, but a few years later, feels the long-term mainstream + hyperscalar is more like: -- Mainstream: Updated GPUs for general ETL (see: https://rapids.ai https://rapids.ai for replacing spark/pandas/sql/flink/etc. w/ streaming GPU ETL in various convenience formats), w/ assumption of continued hw/sw co-design by Nvidia as more of the data stack than just some neural nets get subsumed -- Some experimental work on FPGAs... -- Hyperscalar / bigshops: ... FPGAs mostly for then getting ASICs for the same thing, e.g., sifive's stack, esp. as cloud vendors figure out asics-as-a-service w/ rapid tapeout & 100X more bandwidth. Still easily a few years away pragmatically tho. But if you're say Netflix and the dev cost of doing this stuff drops say ~10X and you get 1-10% cost savings... more than pays for itself. Wall St. tried GPUs years ago and gave up b/c of usability vs payoff, so FPGAs are still in the middle, yet as tool chain improves, the GPU toolchain is now ~there, and not far for ASICs.
- cma 7y ago
  Possibly leaked here: https://www.youtube.com/watch?v=YGTZr6bmNmk&t=18m55s https://www.youtube.com/watch?v=YGTZr6bmNmk&t=18m55s PS5 is supposed to be all about instantaneous load times and Sony has a recent patent on selectively dispatching data from storage to an FPGA instead of (or prior to) going to CPU/GPU.
angry_octet 7y ago
It all seems very improbable. FPGAs are great for massive streaming data, real time and low latency. For data searching and operations, not so much. The same problem that plagues GPU offload is even worse for FPGAs -- and by that I mean Amdahl's Law. It is puzzling that they don't mention Intel, who have been trying to figure this out since they sent $17B on Altera. This actually looks pretty good, if insanely hard to develop for and very expensive: https://www.intel.ca/content/www/ca/en/products/programmable/fpga/agilex.html https://www.intel.ca/content/www/ca/en/products/programmable... The talk of compilers that will take 'high level' languages like C++ and emit logic is, IME, complete rubbish. I mean, it is possible, but it is rubbish logic design. Slow, glitchy, inefficient. Adding pragmas to make the compiler magic work is an art form even trickier than writing VHDL, and requires understanding both.

87 points by matt_d 7y ago

The DPU (Data Processing Unit) which is specialist unit like the GPU but for data tasks like sorting, grouping will be a reality soon!

lmeyerov 7y ago
It's a tough space.. seems more economically feasible to just slightly update GPUs for it, similar to what's happening for ML/tensors/etc, and for the rest, FPGAs for prototyping => ASICs for deployment. We were originally building on OpenCL to keep this path open, but a few years later, feels the long-term mainstream + hyperscalar is more like: -- Mainstream: Updated GPUs for general ETL (see: https://rapids.ai https://rapids.ai for replacing spark/pandas/sql/flink/etc. w/ streaming GPU ETL in various convenience formats), w/ assumption of continued hw/sw co-design by Nvidia as more of the data stack than just some neural nets get subsumed -- Some experimental work on FPGAs... -- Hyperscalar / bigshops: ... FPGAs mostly for then getting ASICs for the same thing, e.g., sifive's stack, esp. as cloud vendors figure out asics-as-a-service w/ rapid tapeout & 100X more bandwidth. Still easily a few years away pragmatically tho. But if you're say Netflix and the dev cost of doing this stuff drops say ~10X and you get 1-10% cost savings... more than pays for itself. Wall St. tried GPUs years ago and gave up b/c of usability vs payoff, so FPGAs are still in the middle, yet as tool chain improves, the GPU toolchain is now ~there, and not far for ASICs.
cma 7y ago
Possibly leaked here: https://www.youtube.com/watch?v=YGTZr6bmNmk&t=18m55s https://www.youtube.com/watch?v=YGTZr6bmNmk&t=18m55s PS5 is supposed to be all about instantaneous load times and Sony has a recent patent on selectively dispatching data from storage to an FPGA instead of (or prior to) going to CPU/GPU.

angry_octet 7y ago

It all seems very improbable. FPGAs are great for massive streaming data, real time and low latency. For data searching and operations, not so much. The same problem that plagues GPU offload is even worse for FPGAs -- and by that I mean Amdahl's Law. It is puzzling that they don't mention Intel, who have been trying to figure this out since they sent $17B on Altera. This actually looks pretty good, if insanely hard to develop for and very expensive: https://www.intel.ca/content/www/ca/en/products/programmable/fpga/agilex.html https://www.intel.ca/content/www/ca/en/products/programmable... The talk of compilers that will take 'high level' languages like C++ and emit logic is, IME, complete rubbish. I mean, it is possible, but it is rubbish logic design. Slow, glitchy, inefficient. Adding pragmas to make the compiler magic work is an art form even trickier than writing VHDL, and requires understanding both.