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Indeed, after working at Tesla for awhile. While the core is great, I think the biggest contributors to the success are a few decisions outside of the design o
by sliken 7y ago
Indeed, after working at Tesla for awhile.
While the core is great, I think the biggest contributors to the success are a few decisions outside of the design of the Zen core.
One is an investment back in the Opteron days for an efficient, scalable, low power, low latency, high performance serial interconnect. This is a key enabler for the new chiplet strategy that has paid off so handsomely for AMD. Now a single piece of silicon can scale from low end Ryzen through the highest end servers without having to divide their limited R&D budget across numerous different designs.
Additionally selling off global foundries enables them to pick the best fab per generation, something that Intel can't, or at least hasn't done.
So Intel had a set back on the fab where the difficulty (chip yield) is increased by their larger chips. While AMD can switch fabs (they switched from global foundries to TMSC at 7nm) and make much smaller chips. The top of the line Epyc chip has 9 chips inside (I/O + 8 CPU chiplets).
This positions AMD Particularly well for the future, they could now rev the I/O chip for DDR5, more memory channels, or any other performance tweak without having to re-engineer the CPU chiplets.
It also doesn't require all the chip related technologies to move in sync. The I/O chiplet is actually made on an older process than the CPU chiplets. If the PCI-e 4 I/O chip was late, AMD could have shipped a PCI-e 3 I/O chiplet. If mid cycle PCI-e 5 becomes a must have AMD would have much less engineering to fix it.
- snuxoll 7y agoPCIe generations are the ONE thing AMD cannot easily rollback or advance out of cycle, since it’s used as the interconnect between everything on the die.
- sliken 7y agoReally? The Infinity Fabric (current generation that evolved from hypertransport) is a cache coherent serial network that can also do PCI-e (non-cache coherently). This can be swapped on a per serial connection basis as needed. Seems like they could rev the PCI-e side without changing the IF side. The I/O chip has separate connections for off chip, so they could use PCI-5 there and not change the connections to any of the CPU chipets. At least it seems that way... corrections?
- wtallis 7y agoThe PCIe and IF connections are basically two MACs sharing the same PHY, and the PHY is the hard part to speed up. There's not really a plausible way that AMD could end up in a situation where they would have reason to boost the speed of just one out PCIe or off-package IF. And the on-package IF PHY between the IO die and the CPU chiplets is easier to get working at a given speed than the off-package version (though I don't remember off the top of my head if they are still using two separate PHY designs on the current generation). So by the time they've got an upgraded IO die with PCIE 5/6/etc., it's pretty much guaranteed that they will be ready to bump up the IF link speed to match.
- AndriyKunitsyn 7y agoGosh, modern hardware is so interesting, yet I know almost nothing about it! What is “serial interconnect”, is it the thing that connects CPU cores?
- d3ckard 7y agoChiplets, not cores(well, precisely cores as well, but the key tech is ability to connect chiplets). Relevant article: https://en.wikichip.org/wiki/amd/infinity_fabric https://en.wikichip.org/wiki/amd/infinity_fabric