Probably unpipelined RISC designs with exclusively single-cycle instructions. The instruction decoder just consists of setting a bunch of multiplexers to the ri

Probably unpipelined RISC designs with exclusively single-cycle instructions. The instruction decoder just consists of setting a bunch of multiplexers to the right states for that instruction. The distinction might be whether the instruction breaks up into a sequence of discrete internal operations. Implementing this as a hardwired state machine is an optimization.