3 ms·
The two MMUs use the same page table. There is only one page table root pointer (actually two: one for user mode and one for kernel mode). But there are two tra
by tralarpa 7y ago
The two MMUs use the same page table. There is only one page table root pointer (actually two: one for user mode and one for kernel mode). But there are two translation caches for code and data (usually called TLB; called ATC in the 68040).
However, there are separate configuration registers for code and data address space that can be used to define which parts of the virtual address space should be translated and which parts are directly mapped to physical addresses without translation. Therefore, strictly spoken, the instruction address space is not necessarily identical to the data address space, despite having only one page table.
- tralarpa 7y agoBy the way, the possible difference between instruction and data address space can have interesting effects. Amiga programmers, do you remember the (bad) habit of putting data fields directly into the code? Like this fragment: ... jsr OpenLibrary(a6) move.l d0, gfxbase rts gfxbase dc.l 0 Imagine now what could happen in the above move.l instruction if the address "gfxbase" is translated differently from the addresses of the instructions :)
- immigrantsheep 7y agoOoh good times :)