3 ms·
Do you have a source for that? Are you talking about accessing internal SRAM, internal Flash, or external memory?
by blackguardx 7y ago
Do you have a source for that? Are you talking about accessing internal SRAM, internal Flash, or external memory?
- londons_explore 7y agoAny architecture with a CPU cache is generally not cycle accurate (since at the time you compile your code you can't fully predict if your data will be in the cache or not). Many pipelined architectures do not define in datasheets exactly what can cause a pipeline stall - usually they provide rough guidance, but not information about corner cases. Branch prediction likewise is rarely fully defined in the datasheets. Some architectures have some operations which are data dependant - for example, "division takes 6-8 cycles". The software developer can't be sure it will be 6, 7, or 8, and if they were to measure performance, they'd be relying on undefined performance behaviour, since a new revision of the same model of chip could change performance. Also, most architectures with DMA aren't cycle accurate because the SRAM is single-ported, so you get a CPU stall if you happen to read memory in the same cycle as a hardware device needs more data.