3 ms·

Thanks for the examples. This is helpful. I can't help but wonder if you or anyone else might be to elaborate on your last point: >"Instruction-to-microcode tr

Thanks for the examples. This is helpful. I can't help but wonder if you or anyone else might be to elaborate on your last point: >"Instruction-to-microcode translation is, unfortunately, not as simple as a (single) table lookup on x86_64 ;)" Is the because of the overloading or are there other reasons it's not as simple as a LUT? Cheers.

woodruffw 7y ago
Overloading and variable-length instructions are the two big reasons that I can think of, off the top of my head. That's pushing the limits of my understanding of how decoding and microcode generation work on-silicon, though.
jcranmer 7y ago
Reading Appendix A of the x86 instruction manual, which lists the opcode maps of the x86 instruction set. Section A.4 in particular gives strong insight into the answer to your question--several opcodes are represented by varying the register bits in the Mod/RM byte. For example, opcode 0f01 is actually several opcodes depending on the Mod/RM byte. If the Mod/RM byte indicates a memory operand, then it's a SGDT, SIDT, LGDT, LIDT, LMSW, or INVLPG instruction (depending on what the first register number is). If it's a register-register form, it can be any one of 17 other instructions depending on the pair of registers.